1. general description the 74lvc1g57-q100 provides configurable mu ltiple functions. eight patterns of 3-bit input, determine the output state. the user can choose the logic functions and, or, nand, nor, xnor, inverter and buffer. all inputs can be connected to v cc or gnd. inputs can be driven from either 3.3 v or 5 v devi ces. this feature allows the use of this device in a mixed 3.3 v and 5 v environment. this device is fully specified for pa rtial power-down ap plications using i off . the i off circuitry disables the output, preventin g the damaging backflow current through the device when it is powered down. all inputs (a, b and c) are schmitt trigger inpu ts that can transform slowly changing input signals into sharply defined, jitter-free output signals. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 1.65 v to 5.5 v ? 5 v tolerant input/ output for interfacing with 5 v logic ? high noise immunity ? complies with jedec standard: ? jesd8-7 (1.65 v to 1.95 v) ? jesd8-5 (2.3 v to 2.7 v) ? jesd8b/jesd36 (2.7 v to 3.6 v). ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? ? 24 ma output drive (v cc =3.0v) ? cmos low power consumption ? latch-up performance exceeds 250 ma ? direct interface with ttl levels ? inputs accept voltages up to 5 v ? multiple package options 74lvc1g57-q100 low-power configurable multiple function gate rev. 1 ? 15 april 2014 product data sheet
74lvc1g57-q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rig hts reserved. product data sheet rev. 1 ? 15 april 2014 2 of 16 nxp semiconductors 74lvc1g57-q100 low-power configurable multiple function gate 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning table 1. ordering information type number package temperature range name description version 74LVC1G57GW-Q100 ? 40 ? cto+125 ? c sc-88 plastic surface-mounted package; 6 leads sot363 74lvc1g57gv-q100 ? 40 ? cto+125 ? c sc-74 plastic surface-mounted package; 6 leads sot457 table 2. marking type number marking code [1] 74LVC1G57GW-Q100 yc 74lvc1g57gv-q100 v57 fig 1. logic symbol y c b a 6 1 3 4 001aab583 fig 2. pin configuration sot363 and sot457 / 9 & |